The present invention relates to a semiconductor chip and a stacked semiconductor package having the same.
In general, a semiconductor chip has a cell region in which integrated circuits are formed and a peripheral region which is defined outside the cell region and in which input/output pads for controlling input/output of data are formed, depending upon a chip design. The input/output pads which are formed in the peripheral region are electrically connected with input/output circuits and form electrical contacts with an outside.
In the case of semiconductor chips which have through electrodes, since input/output pads for connecting the through electrodes of an upper semiconductor chip and the through electrodes of a lower semiconductor chip are added, the semiconductor chips should have peripheral regions which have increased sizes so that the sizes of the semiconductor chips increase. One problem is that if the size of a semiconductor chip increases, the number of dies manufactured per wafer decreases and as a result the manufacturing costs increase.
In order to prevent or minimize size increases in the semiconductor chips, the sizes of the input/output pads should be decreased. However, input/output pads should have basic minimum size restrictions for enabling electric die sorting test to be performed to prove the reliability of the semiconductor chip and for forming electrical interconnections. Accordingly, physical limitations exist in decreasing the sizes and the pitches of the input/output pads. As a consequence, it is difficult to decrease of the size of peripheral regions in which the input/output pads are formed because these physical limitations exist in decreasing the size of the semiconductor chip.